1. Field of the Invention
The present invention relates to semiconductor devices having check patterns or test element groups (TEG) for the purpose of testing of electric characteristics thereof required in development, design, and process check in manufacturing.
The present application claims priority on Japanese Patent Application No. 2007-117071, the content of which is incorporated herein by reference.
2. Description of the Related Art
P/W tests (i.e. probe tests and/or wafer tests) have been conventionally performed to achieve operation checks and characteristic checks with respect to chips formed on wafers, thus making determination as to qualities of chips. They are important factors of inspection to check completions of semiconductor devices or semiconductor memories such as DRAM.
In the present technology, test element groups (TEG) for the purpose of characteristic checks are formed on scribing lines drawn between chips adjoining together on a wafer. There are provided various types of test element groups such as transistors (e.g. MOS transistors and bipolar transistors), memory cells, and resistors for measuring resistances of diffusion layers and lines, which are incorporated in the product circuitry of semiconductor memories.
However, it is very difficult to use probe cards (specified for the purpose of wafer tests such as pass/fail tests of semiconductor chips) with respect to test element groups formed on scribing lines.
In order to realize testing of test element groups formed on scribing lines, it is necessary to use probe cards specified for the purpose of testing test element groups; and it is necessary to perform checking processes specified for the purpose of characteristic checks by test element groups, thus achieving characteristic checks on semiconductor devices.
Compared with test devices for the purpose of wafer tests in mass production, test devices specified for the purpose of characteristic checks do not have multi-check functions for simultaneously checking multiple chips; hence, it is unrealistic to employ them because it takes enormous time to check all check points of wafers.
To solve the aforementioned drawback, test element groups are formed inside of semiconductor chips instead of scribing lines, thus allowing characteristic checks to be performed by use of probe cards and test devices having multi-check functions in testing of wafers in mass production. This technology is disclosed in Patent Document 1, for example.
Patent Document 1: Japanese Unexamined Patent Application Publication No. H09-213901
Patent Document 1 teaches a semiconductor memory in which multiple pads are specifically formed and come in contact with probe tips of probe cards. This semiconductor device suffers from reliability with regard to test results due to parasitic resistances of lines and circuits for selecting check patterns in test element groups.
In addition to parasitic resistances, this semiconductor memory additionally needs protection resistors (having high resistances) attached to check patterns in order to protect check patterns from being destroyed during testing of test element groups. Dispersions of protection resistors may degrade precision and reliability in testing.
When test element groups are formed on chips instead of scribing lines after the semiconductor device is encapsulated in a package, it is necessary to use pads specified for the purpose of testing test element groups. In manufacturing, wire bonding is not performed on these pads; hence, after the semiconductor device is encapsulated in a package, it is impossible to perform testing of test element groups.